The past few decades have seen many shifts in electronics and semiconductor packaging that have impacted the entire semiconductor industry. The introduction of surface-mount technology (SMT), such as ball grid array (BGA), land grid array (LGA), and similar types of packages, were generally important steps for high-throughput assembly of a wide variety of integrated circuit (IC) devices, while, at the same time, allowing reduction of the pad pitch on the printed circuit board. Conventionally packaged ICs have a structure basically interconnected by fine gold wire between metal pads on the die and electrodes spreading out of molded resin packages. Dual Inline Package (DIP) and Quad Flat Package (QFP) are fundamental structures of current IC packaging. However, increased pin count peripherally designed and arranged around the package typically results in too short of a pitch of lead wire, yielding limitations in board mounting of the packaged chip.
Chip-scale or chip-size packaging (CSP), BGA, LGA, and the like are just some of the solutions that enable dense electrode arrangement without greatly increasing the package size. CSP provides for wafer packaging on a chip-size scale. CSP typically results in packages within 1.2 times the die size, which greatly reduces the potential size of devices made with the CSP material. Although these advances have allowed for miniaturization in electronic devices, the ever-demanding trend toward even smaller, lighter, and thinner consumer products have prompted even further attempts at package miniaturization.
To fulfill market demands toward increased miniaturization and functionality, WLCSP has been introduced in recent years for generally increasing density, performance, and cost-effectiveness, while decreasing the weight and size of the devices in the electronic packaging industry. In WLCSP, the packaging is typically generated directly on the die with contacts provided by BGA, bump electrodes, LGA, and the like. Recent advanced electronic devices, such as mobile phones, mobile computers, camcorders, personal digital assistants (PDAs), and the like, utilize compact, light, thin, and very densely packaged ICs. Using WLCSP for packaging smaller die size devices with lower numbers of pins, corresponding to larger number of chips on one wafer, is, therefore, usually advantageous and cost-effective.
During the typical manufacturing process, a silicon wafer is processed to include many separate dies on the same wafer. Once the processing of the circuitry and packaging features has been finished, die saws cut the wafer to separate each die. During this process, a wafer with up to thousands of circuits is cut into individual pieces, each called a die. In between the functional parts of the circuits, a thin non-functional spacing, called the scribe, is generally provided, where a saw can safely cut the wafer without damaging the circuit. The width of the scribe is typically very small, usually around 100 μm. Usually the dicing is performed with a highly-accurate water-cooled circular saw having diamond-tipped teeth.
One disadvantage of the prior art is that the wafer may sometimes crack or splay at the die edge, thus, diminishing the integrity and reliability of the integrated circuit (IC) chip. Faulty die diminish the return on investment to the semiconductor manufacturers and, thus, raises the costs for each individual IC die. In some applications, a die saw groove is often created by a laser within the boundary regions of the wafer in order to make the scribe area less prone to cracking or splaying during the cutting process. However, while the laser-cut die saw groove lowers the chance of splaying or cracking, such damage continues to be an occurrence.
One method for separating or singulating the individual die regions on a wafer is described in U.S. Pat. No. 6,717,245 to Kinsman, et al. (hereinafter Kinsman). Kinsman describes a process in which a die saw or wet etching cuts channels between the individual die down through an active layer of the wafer. These channels are then filled with an encapsulating material that forms a hermetical seal around the active regions of each die. Another die saw is then used to cut through each channel to separate or singulate each die. The encapsulating material assists in preventing splaying or cracking of the wafer, although such damage generally continues simply by virtue of the operation of the die saw on the wafer.
In CSP, an encapsulating layer of some type of resin or polymer typically seals the wafer, including the die saw grooves. Another method of die cutting CSP wafers is described in U.S. Pat. No. 6,107,164, to Ohuchi (hereinafter Ohuchi). In Ohuchi, a diamond blade saw is used to cut grooves into the wafer. Ohuchi teaches that the grooves are preferably cut to a depth of about two-thirds the depth of the wafer. Thereafter the encapsulating layer is applied. The encapsulating layer, thus, fills the grooves. In the separation process, Ohuchi describes that the back of the wafer is polished to remove the silicon and reveal the grooves filled with the encapsulating material. After the backside has been thinned, a narrow blade is used to cut the wafer at the exposed grooves. Again, the addition of the encapsulating layer to the saw grooves assists in preventing some damage to the die caused by the wafer saws. However, damage continues because the wafer saws still operate to separate or singulate the die from the wafer.